Reference is made to FIG. 1 which shows a schematic diagram of a standard six transistor (6T) static random access memory (SRAM) cell 10. The cell 10 includes two cross-coupled CMOS inverters 12 and 14, each inverter including a series connected p-channel and n-channel MOSFET transistor pair. The inputs and outputs of the inverters 12 and 14 are coupled to form a latch circuit having a true data storage node 16 and a complement data storage node 18. The cell 10 further includes two transfer (passgate) transistors 20 and 22 whose gate terminals are coupled with a wordline node and are controlled by the signal present at the wordline node (WL). Transistor 20 is source-drain connected between the true data storage node 16 and a node associated with a true bitline (BLT). Transistor 22 is source-drain connected between the complement data storage node 18 and a node associated with a complement bitline (BLC). The source terminals of the p-channel transistors in each inverter 12 and 14 are coupled to receive a high supply voltage (for example, VDD) at a high voltage node VH, while the source terminals of the n-channel transistors in each inverter 12 and 14 are coupled to receive a low reference voltage (for example, GND) at a low voltage node VL. The high supply voltage VDD at the node VH and the low reference voltage GND at the node VL comprise the power supply set of voltages for the cell 10.
In an integrated circuit including the SRAM cell 10, this power supply set of voltages may be received at pins of the integrated circuit, or may instead be generated on chip by a voltage regulator circuit which receives some other set of voltages from the pins of the chip. The power supply set of voltages at the nodes VH and VL are conventionally applied to the SRAM cell 10 at all times that the cell/integrated circuit is operational.
The reference above to a six transistor SRAM cell 10 of FIG. 1 for use as the data storage element is made by way of example only, it being understood to those skilled in the art that the cell 10 could alternatively comprise a different data storage element. The use of the term SRAM cell will accordingly be understood to refer any suitable memory cell or date storage element, with the circuitry, functionality and operations presented herein in the exemplary context of a six transistor SRAM cell.
SRAM performance is constrained by two independent operations. The first operation is the read operation measured by the time between the read triggering signal and the presence of a valid output. The second operation is the write operation measured by the time between the write triggering signal and a next possible write (or read) triggering signal to ensure a proper write (and a subsequent read).
Those skilled in the art recognize a move in the electronics industry to lower supply voltages for circuits. This is especially the case with respect to memory cells such as SRAM cells. Low voltage functionality for SRAM cells is typically managed by: decoupling the read and write ports of the cell so as to remove the known storage node stability constraint encountered during a read; and sizing the read and write ports independently of each other so as to ensure a correctness of both the read and write operations.
Due to write-margin constraint, the write port of the SRAM cell is sized such that the slowest passgate n-channel transistor will overcome the strength of the fastest (feedback) pull-up p-channel transistor. However, so as to manage a design with a low occupied area, and also to limit current leakage, those skilled in the art understand that the passgate n-channel transistor cannot be very large. This, then, necessitates a cell design where the p-channel transistor is not very strong. With this compromise, the p-channel transistor ends up defining the write time of the cell and limits overall SRAM performance at low supply voltages.
There is a need in the art to address the foregoing problems and constraints.